1. Field of the Invention
The present invention relates to an FM demodulator circuit for use in an FM receiver or the like and, more particularly, to a quadrature FM demodulator circuit.
2. Description of the Related Art
FIG. 8 is a circuit diagram showing a conventional quadrature FM demodulator circuit suitable for an integrated circuit.
In FIG. 8, V.sub.IN represents a signal voltage of an FM input signal source 1. A differential amplifier 2 amplifies an FM signal supplied from the FM input signal source 1. A phase shift circuit 3 shifts a phase of a carrier signal as a center frequency of an FM signal supplied from the differential amplifier 2 by 90.degree. . A double balance type differential multiplier circuit 4 multiplies a signal output from the phase shift circuit 3 and a signal output from the differential amplifier 2. The multiplier circuit 4 thus outputs a demodulation output voltage V.sub.out.
In the differential amplifier 2, the bases of NPN transistors Q.sub.1 and Q.sub.2 constituting a differential pair are connected to both ends of the FM input signal source 1, and the emitters of the NPN transistors are connected to each other and grounded through a bias current source I.sub.1. Resistive elements R.sub.1 and R.sub.2 are connected between the NPN transistors Q.sub.1 and Q.sub.2 and a power source +B, respectively The power source +B is at an alternating-current-like reference potential. A bias voltage source V.sub.B1 is connected between the base of the NPN transistor Q.sub.2 and the power source +B.
In the phase shift circuit 3, one end of a capacitive element C.sub.1 is connected to the collector of the NPN transistor Q.sub.1, and a capacitive element C.sub.2, an inductive element L.sub.1, and a resistive element R.sub.3 are connected in parallel between the other end of the capacitive element C.sub.1 and the power source +B.
In the multiplier circuit 4, first balance input terminals 5 are connected to the collectors of the NPN transistors Q.sub.1 and Q.sub.2 which serve as output terminals of the differential amplifier 2, and second balance input terminals 6 are connected to the power source +B and the other end of the capacitive element C.sub.1 which serves as an output terminal of the phase shift circuit 3. The first balance input terminals 5 are connected to one end of each of capacitive elements C.sub.4 and C.sub.5 for interrupting direct current. The other ends of the capacitive elements C.sub.4 and C.sub.5 are connected to one end of each of resistive elements R.sub.6 and R.sub.7, respectively. The other ends of the resistive elements R.sub.6 and R.sub.7 are grounded through a bias voltage source V.sub.B2.
The other ends of the capacitive elements C.sub.4 and C.sub.5 are respectively connected to the bases of NPN transistors Q.sub.3 and Q.sub.4 constituting a differential pair The emitters of the NPN transistors Q.sub.3 and Q.sub.4 are grounded through a bias current source I.sub.2. The collector of the NPN transistor Q.sub.3 is connected to the emitters of NPN transistors Q.sub.5 and Q.sub.6 constituting a differential pair, and the collector of the NPN transistor Q.sub.4 is connected to the emitters of NPN transistors Q.sub.7 and Q.sub.8 constituting a differential pair. The bases of NPN transistors Q.sub.5 and Q.sub.8 are connected to the one of the second balance input terminals 6 and those of NPN transistors Q.sub.6 and Q.sub.7 are connected to the other second balance input terminal 6. The collectors of NPN transistors Q.sub.5 and Q.sub.7 are connected to the power source +B, and those of NPN transistors Q.sub.6 and Q.sub.8 are connected to the power source +B through a low pass filter 7. The low pass filter 7 includes a resistive element R.sub.4 and a capacitive element C.sub.3.
In FIG. 8, the circuits other than the phase shift circuit 3 constitute an integrated circuit, and the phase shift circuit 3 is externally connected to the integrated circuit.
If output voltages of the differential amplifier 2 are represented by V.sub.1 and V.sub.2, an output voltage of the phase shift circuit 3 is represented by V.sub.3, a signal voltage V.sub.x1 of the first balance input terminals 5 of the multiplier circuit 4 and a signal voltage V.sub.x2 of the second balance input terminals 6 thereof are given by the following equations, respectively. EQU V.sub.x1 =V.sub.1 -V.sub.2 EQU V.sub.x2 =V.sub.3
The multiplier circuit 4 thus multiplies an FM signal supplied from the differential amplifier 2 to the first balance input terminals 5 by an FM signal supplied from the phase shift circuit 3 to the second balance input terminals 6. The low pass filter eliminates a carrier component and a harmonic component included in an output signal of the multiplication and then outputs a demodulation signal.
FIG. 9 shows an equivalent circuit for analyzing the phase characteristics of the circuit shown in FIG. 8 from which an influence of each of the transistors is removed, and FIG. 10 shows a phase difference .PHI. between the signal voltage V.sub.x1 and signal voltage V.sub.x2 with respect to a carrier frequency fin of the equivalent circuit shown in FIG. 9.
In FIG. 9, V.sub.IN' indicates an anti-phase voltage of the signal voltage V.sub.IN of the FM input signal source 1, and the capacitive elements C.sub.1 and C.sub.2 of the phase shift circuit 3 have capacitances of 6.8 pF and 80 pF, respectively, the inductive element L.sub.1 has an inductance of 2.77 .mu.H, and the resistive element R.sub.3 has a resistance of 6.8 k.OMEGA..
The characteristic shown in the upper portion of FIG. 10 is the phase difference .PHI. and is represented using the resistances of the resistive elements R.sub.1 and R.sub.2 of the differential amplifier 2 as parameter. The characteristics shown in the lower portion of FIG. 10 is the linearity of the phase difference .PHI. obtained by differentiating the phase difference .PHI. by the carrier frequency fin.
What is noted in the characteristics shown in FIG. 10 is that an inflection point of the linearity of the phase difference .PHI. is shifted from a phase difference .PHI. of 90.degree. as the resistances of the resistive elements R.sub.1 and R.sub.2 of the differential amplifier 2 increases. The constants of the phase shift circuit 3 are set so that the phase difference .PHI. is 90.degree. when the carrier frequency fin is the central frequency of the FM signal. For this reason, if the resistances of the resistive elements R.sub.1 and R.sub.2 of the differential amplifier 2 increase, the waveform of a demodulation output is asymmetric in coordinates and the demodulation output increases in distortion.
It is therefore necessary for the conventional quadrature FM demodulator circuit shown in FIG. 8 that the resistances of the resistive elements R.sub.1 and R.sub.2 are made as small as possible in order to reduce the distortion of the demodulation output. Since, however, the current value of the bias current source I.sub.1 needs to be remarkably increased to keep the amplitudes of output voltages V.sub.1 and V.sub.2 of the differential amplifier 2 at predetermined values, a power loss greatly increases and accordingly the conventional quadrature FM demodulator circuit is unsuitable for a power save type FM demodulator circuit.